1. Field of the Invention
The invention relates to a charge pump circuit used for a PLL circuit (phase locked loop circuit) and a PLL circuit in which the charge pump circuit is used.
2. Description of the Prior Art
FIG. 12 shows a PLL circuit which comprises a digital phase comparator 210, a charge pump circuit 220, a lowpass filter 300 and a voltage control oscillator 400. The charge pump circuit 220 is connected to an output side of a digital phase comparator 210 in a PLL circuit to drive the low pass filter.
Charge pump circuit 220 draws or supplies current from node N1 according to up-signal UP and down-signal DOWN which are inputted from the up-terminal and the down-terminal of a digital phase comparator, respectively.
Digital phase comparator 210 receives input signal A and input signal B, and then makes the up-signal UP and the down-signal DOWN active state/non-active state, respectively, according to a phase difference between input signal A and input signal B. The digital phase comparator 210 then outputs up-signal UP and down-signal DOWN into charge pump circuit 220.
Charge pump circuit 220 comprises constant current sources 221 and 222 and switch means 223 and 224, which are inserted between power source Vcc and an earth. Switch means 223 turns on when up-signal UP is in active state and supplies node N1 which is an output portion with constant current I.sub.0 from constant current source 221. Switch means 224 turns on when down-signal DOWN is in an active state and draws out constant current I.sub.0 from node N1 by constant current source 222.
FIG. 19 is a timing chart which shows an operation of charge pump circuit 220 according to input signal A and input signal B. As shown in FIG. 19, while rising edge of input signal B is behind rising edge of input signal A, up-signal UP is activated and supplies node N1 with constant current I.sub.0 (+I.sub.0). While rising edge of input signal B precedes rising edge of input signal A, down-signal DOWN is activated and constant current I.sub.0 is drawn out (-I.sub.0) from node N1.
Lowpass filter 300, having capacitors 311 and 313 and resistor 312, smoothes voltage which is provided from node N1 in charge pump circuit 220 and outputs control voltage SV to voltage control oscillator 400. Voltage control oscillator 400 outputs signal B whose frequency is in proportion to control voltage SV and sends signal B to one input terminal of the digital phase comparator 210.
In such a PLL circuit, (1) when the phase of input signal B is behind the phase of input signal A, digital phase comparator 210 outputs up-signal UP in the active state. Thereby, lowpass filter 300 raises control voltage SV in order to raise frequency of output signal B of voltage control oscillator 400. (2) When the phase of input signal B precedes the phase of input signal A, digital phase comparator 210 outputs down-signal DOWN in the active state. Thereby, lowpass filter 300 lowers control voltage SV in order to lower frequency of output signal B of voltage control oscillator 400. Consequently, the PLL circuit operates so that phase difference between the input signal A and the input signal B decreases. Ultimately, the input signal B, whose phase is synchronized with the input signal A, is provided.
FIG. 13 is a circuit diagram which shows a concrete internal construction of charge pump circuit 220. As shown in FIG. 13, a base of PNP bipolar transistor 23 and a base of PNP bipolar transistor 25 are connected mutually to comprise a current mirror circuit. An emitter of PNP bipolar transistor 23 is connected to power source Vcc through resistor 22. An emitter of PNP bipolar transistor 25 is connected to power source Vcc through resistor 24. A collector of PNP bipolar transistor 25 is connected to output terminal 20.
NPN bipolar transistor 26 and NPN bipolar transistor 27 mutually construct a differential pair and respective bases of NPN bipolar transistors 26 and 27 receive down-signal DOWN and inverted down-signal/DOWN (bar codes in figures correspond to "/" in the specification). A collector of NPN bipolar transistor 26 is connected to output terminal 20 and a collector of NPN bipolar transistor 27 is connected to power source Vcc. Emitters of NPN bipolar transistors 26 and 27 are connected in common.
NPN bipolar transistor 28 and NPN bipolar transistor 29 mutually construct a differential pair and respective bases of NPN bipolar transistors 28 and 29 receive up-signal UP and inverted up-signal/UP. A collector of NPN bipolar transistor 28 is connected to power source Vcc and a collector of NPN bipolar transistor 29 is connected to output terminal 20. Emitters of NPN bipolar transistors 28 and 29 are connected in common.
Bases of NPN bipolar transistors 32, 35 and 36 are connected in common to a base of NPN bipolar transistor 30 whose base is connected to its collector. Thereby, NPN bipolar transistors 32, 35 and 36 are connected to NPN bipolar transistor 30 to construct a current mirror circuit.
A collector of NPN bipolar transistor 30 is connected to power source Vcc through constant current source 13, and an emitter of NPN bipolar transistor 30 is grounded through resistor 31. A collector of NPN bipolar transistor 32 is connected to a collector and a base of NPN bipolar transistor 23, while an emitter of NPN bipolar transistor 32 is grounded through resistor 33. A collector of NPN bipolar transistor 35 is connected to common emitters of NPN bipolar transistors 26 and 27, and an emitter of NPN bipolar transistor 35 is grounded through resistor 34. A collector of NPN bipolar transistor 36 is connected to common emitters of NPN bipolar transistors 28 and 29, while an emitter of NPN bipolar transistor 36 is grounded through resistor 37.
Transistor sizes of PNP bipolar transistors 23 and 25 are the same, while transistor sizes of NPN bipolar transistors 26.about.36 are the same.
In such a charge pump circuit, since NPN bipolar transistors 32, 35 and 36 are connected to NPN bipolar transistor 30 as current mirror, respective collector current of PNP bipolar transistor 25, respective collector currents of NPN bipolar transistor 35 and NPN bipolar transistor 36 are equal to constant current I.sub.0 supplied from constant current source 13.
On the other hand, when input signal B is behind input signal A as shown in FIG. 19, up-signal UP of digital phase comparator 210 is in an active state (H level), while down-signal DOWN is in a non-active state (L level).
In such a circuit, in case that input signal B is behind input signal A as shown in FIG. 19, when up-signal UP (H) and down-signal DOWN (L) are inputted to up-terminal 14 and down-terminal 15 of charge pump circuit 220, respectively, down-signal DOWN (L) and inverted down-signal DOWN (H) are applied to NPN bipolar transistors 26 and 27, respectively. Then, NPN bipolar transistor 26 turns off and NPN bipolar transistor 27 turns on.
On the other hand, up-signal UP (H) and inverted up-signal/UP (L) are applied to NPN bipolar transistors 28 and 29, respectively. Then, NPN bipolar transistor 28 turns on and NPN bipolar transistor 29 turns off. Accordingly, current flows through neither NPN bipolar transistor 26 nor NPN bipolar transistor 29. Therefore, as shown in FIG. 16, constant current I.sub.0 is supplied from output terminal 20 only from a collector of PNP bipolar transistor 25.
As shown in FIG. 19, in case of input signal B precedes input signal A, when up-signal UP (L) and down-signal DOWN (H) are inputted to up-terminal 14 and down-terminal 15 of charge pump circuit 220, respectively, down-signal DOWN (H) and inverted down-signal/DOWN (L) are applied to NPN bipolar transistors 26 and 27. Then, NPN bipolar transistor 26 turns on and NPN bipolar transistor 27 turns off.
On the other hand, up-signal (L) and inverted up-signal (H) are applied to NPN bipolar transistors 28 and 29, respectively. Then, NPN bipolar transistor 28 turns off and NPN bipolar transistor 29 turns on. Accordingly, current flows through both NPN bipolar transistor 26 and NPN bipolar transistor 29. Therefore, as shown in FIG. 17, constant current I.sub.0 is supplied to output terminal 20 from a collector of PNP bipolar transistor 25, while 2I.sub.0 is drawn out from NPN bipolar transistors 26 and 29. Accordingly, constant current I.sub.0 is drawn out from output terminal 20, since I.sub.0 -2I.sub.0 =-I.sub.0.
In case that input signal A synchronizes with input signal B, up-signal UP (L) and down-signal DOWN (L) or up-signal UP (H) and down-signal DOWN (H) are inputted. As shown in FIGS. 18A, 18B, constant current I.sub.0 is supplied from output terminal 20 from PNP bipolar transistor 25, and the same amount of constant current I.sub.0 is drawn out by either NPN bipolar transistor 26 or 27. Accordingly, current is not supplied from output terminal 20, since I.sub.0 -I.sub.0 =0.
As described above, charge pump circuit 220 supplies or draws out constant current I.sub.0 via output terminal 20 according to respective modes of up-signal UP and down-signal DOWN of digital phase comparator 210. FIG. 15 shows a table which shows the above mentioned operation, and shows relationship between switch state and output current at each mode in a conventional charge pump circuit.
FIGS. 20A, 20B show how to calculate a dynamic range of output voltage 20 in a conventional charge pump circuit 220. As shown in FIG. 20A, an output voltage range of output terminal 20 in this circuit is calculated by following formula, EQU Vcc-3 V.sub.BE -2 .DELTA.V.sub.R,
where
.DELTA.V.sub.R : voltage which is generated by an emitter resistance of a transistor (about 0.3 V), PA1 V.sub.BE : Voltage between base and emitter of a transistor (about 0.7 V).
As shown in FIG. 20B, upper limit of dynamic range V.sub.UP can be calculated by following formula, ##EQU1## lower limit of dynamic range can be calculated by following formula, ##EQU2##
Accordingly, dynamic range V.sub.D can be calculated by following formula, EQU V.sub.D =upper limit of dynamic range V.sub.UP -lower limit of dynamic range V.sub.DOWN =4 V-1.7 V=2.3 V.
Accordingly, dynamic range in a conventional circuit is affected by base emitter voltage 3.times.V.sub.BE of a transistor connected in three cascade stages between a power source and an earth and the dynamic range is only 2.3 V. The range that VCO can follow its input frequency in a PLL circuit is usually called a lock range of PLL. There is a problem that this lock range gets narrower if output dynamic range of output terminal 20 is small. This phenomenon especially appears conspicuous in reduced voltage operation or low voltage operation of PLL circuit.
The object of the present invention is to provide a charge pump circuit which makes it possible to set a broad dynamic range of output voltage, and to provide a PLL circuit which makes it possible to set a broad dynamic range.